Test Access Circuit for Education

In this paper we present our new educational chip. This chip is one of three chips which were designed for educational purposes within the framework of the IST project REASON. Nowadays the Boundary Scan (BS) has become to be a standard for diagnostic access to the circuits, for in-circuit programming and for several other tasks. The Boundary Scan access is sometimes combined with a scan chain of concatenated peripheral and internal flip-flops. An alternative parallel diagnostic access method is called Random Access Scan (RAS). This diagnostic access is not used in nowadays designs because of difficult routability and higher hardware overhead. In spite of this fact the RAS diagnostic methods to flip-flops of Integrated Circuit (IC) are much less energy consuming than any of the serial diagnostic approaches. In order to demonstrate the RAS diagnostic access method properties we have proposed a simple functional block equipped with a scan chain and the same block with a RAS access. Both parts are controlled by the BS Test Access Port (TAP) controllers. This circuit, with code name TestAccess block, was synthesized in IET Warsaw, manufactured by TIMA-CMP service and in this paper we would like to present the basic chip features.